Assembler 2002

Jokes Magazine Amusing Opcodes

BNE - Branch to Non-Existent code

BNR - Branch for No Reason.

BRA - Branch to Random Address

BVS - Branch to Virtual Subroutine

CLD - CalL a Doctor

CMD - Create Meaningless Data.

DEC - DElete the Code

DRA - Decrement Random Address.

EDR - Emit Deadly Radiation.

JMP - Jump if Memory Present (conditional jump)

LLI - Lose Last Instruction.

PRS - Push Results off Stack.

RIS - Remain In Subroutine.

RTI - Return from the Infinity

SHB - Scramble High order Bit.

TEC - Take Extra time for Calculation

[Mar 4, 2002] BURKS Assembly languages -- the online version of the 6th edition of BURKS, a non-profit set of CD-ROMs for students of Computer Science.

Assembly Language Windows Applications

Microsoft's Macro Assembler, FREE ! ! !

That's right! Microsoft has made their Windows 98 DDK (Device Driver Kit) available from their web site FOR FREE DOWNLOAD! The kit INCLUDES everything you need to build 32-bit Windows Applications in Assembly Language ... including Microsoft's Macro Assembler MASM (ML.EXE) and the 32-bit Linker (LINK.EXE). Grab it NOW before it goes away!

http://www.microsoft.com/ddk/ddk98.asp
or
http://www.microsoft.com/ddk/install98ddk.asp

And ... after you get those version 6.11d files from the DDK, you may want to update them to the latest and greatest version 6.14. You can do that with this much smaller little patch file from Microsoft. Click this link for the file, or see this page for more info:

http://support.microsoft.com/support/kb/articles/Q228/4/54.ASP

Best luck with it ... and if you write something great let me know and I'll put a link to it here ... you never know, maybe Small Is Beautiful software will catch on and I won't become a dinosaur after all!

[Feb 07, 2002] Re- Coroutines was Re- Assembly language formatting

Search Result 38 From: Mark Crispin ([email protected]) Subject: Re: Coroutines was Re: Assembly language formatting Newsgroups: alt.sys.pdp10, alt.folklore.computers View: Complete Thread (11 articles) | Original Format Date: 2000-08-23 13:40:48 PST

On Wed, 23 Aug 2000, David Eppstein wrote:
> When I've written coroutines in C-like languages, the technique I used
> was to make one of the routines look like a subroutine, by writing it as
> a giant switch statement

That technique, although extremely useful, is more of a "finite state
machine" than a "coroutine".

Unfortunately, C doesn't allow you to do coroutines in a portable way; the
ability to change the stack is non-portable by definition.  What you need
to do real coroutining in C is a two-way longjmp(), that does an implicit
setjmp() at the current point priro to returning to the previous setjmp().

> It sure was easier to do real coroutines in PDP-10 assembly though.

That does without saying.  The JSR, JSP, and XPCW instructions were the
coroutine instructions.  There was also JSA/JRA and user-mode JSYS, but
those fell by the wayside.

Probably the most commonly-used coroutine instruction was JSP, since it
worked on all CPUs and did not impinge upon pure code.  It did require the
use of an AC though.  I used JSP coroutining extensively in the device
drivers that I wrote for WAITS and TOPS-20.  The only time I used JSR
coroutining was in a WAITS device driver, where I had to support a
KA10-style BLKI/BLKO device in the interrupt locations.  Even TOPS-20 had
vestigal evidence of that old way of doing interrupts, but that was
ancient history by KL days (and extinct in the KS).

-- Mark --

[Feb 02, 2002]

From: Eric Werme - replace nobody with werme ([email protected]) Subject: Re: Coroutines (was: Compiler.) Newsgroups: alt.folklore.computers, alt.sys.pdp10 View: Complete Thread (13 articles) | Original Format Date: 1998/05/05

[email protected] (Alan Bowler) writes in a.f.c:

>In article <[email protected]> [email protected] writes:
>>
>>Another neat thing that was used was the notion of co-routines.
>>Perhaps somebody more qualified would talk about this? 
>You mean "co-operative multitasking with threads" :-)

Well, there are coroutines that take many instructions to switch between
and there are coroutines that take one instruction.  Barbara was talking
about the latter.  The definition of a coroutine as I heard it is that
the two code paths use the same mechanism to transfer control back and
forth.  Of the many styles of subroutine calls on the PDP-10, JSP ac,addr
is the fastest, as it's the only one that doesn't require a memory store.
Its ISP is something like:

	ac = PC
	PC = effective address [addr in the usual case]

The subroutine return, of course, is:

	JRST (ac)

Here, the efective address is the contents of the register.

The coroutine instruction combined the two:

	JSP ac,(ac)

This essentially exchanged the PC with ac.

There's one big catch here - there can't be unanswered pushes or pops in either
piece of code, this is one reason why many people equate coroutines with
context switches and the exchange of many registers.

I have two good examples to describe.  I'll put the second one in a
separate posting.

I wrote the client side of TOPS-10 TELNET for the Arpanet that ran at
Carnegie Mellon, Harvard, and Rutgers.  Telnet has several multi character
sequences and they can be split across message boundaries.  TOPS-10 made
it easiest for use to get a message at interrupt level, and step through
each octet in sequence, calling the TTY input code as necessary.  However,
parsing the Telnet options is more easily done by code that can call a
subroutine to fetch one character at a time.

So I compromised.  The network side looked something like:

prcmsg:	PUSHJ	P,SAVE1		;Save P1
	MOVE	P1,LAST_PC(F)	;Get PC where telnet left off
	PUSHJ	P,GET_CH	;Get next byte from message
	 JRST	DONE		;None left
	JSP	P1,(P1)		;call telnet processor
	JRST	LOOP

DONE:	MOVEM P1,LAST_PC(F)
	 POPJ	P,

Not too exciting.

The telnet side looked something like:

PRCTEL:	CAIN	T1,IAC		;Telnet escape?
	 JRST	NORMCH		;just text
	JSP	P1,(P1)		;get next character
	CAIGE	T1,MINTEL	;command in range 240 - 255
	 JRST	BAD		;Out of range
	JRST	DISPTBL-MINTEL(T1) ; Dispatch

	...

WONT:	JSP	P1,(P1)		;Get option code
	...

The nice thing about all this was that the telnet processor had no
idea that some of its coroutine calls actually resulted in dismissing
an interrupt.

Another way of looking at this code is to see a state machine where
the PC is the state variable.

A decade later when I was at Alliant, I fielded a phone call from a customer
with a Macintosh machine that was sometimes having trouble with its
Telnet link.  The customer had managed to trace it to telnet commands
split between two TCP messages.  I really tried to be sympathetic, but
I was firm that Alliant's system, while perhaps not being Mac-friendly,
was compliant with the protocols and that I was sure a Macintosh should
be able to handle split telnet commands.

Other architectures have coroutine instructions too.  On the PDP-11:

	JSR Rx,@Rx

The Intel 860 _almost_ has one:

	calli r1

(Calli is like jsp r1,ea in that the return pc is stored in r1.)  However,
the i860 manual says this is a no-no.

I should know if Alpha has one, but I just don't do enough assembly language
here.
--
<>    Eric (Ric) Werme     <> The above is unlikely to contain   <>
<>    ROT-13 addresses:    <> official claims or policies of     <>
<>   <[email protected]>   <> Digital Equipment Corp.            <>
<> <[email protected]> <>  http://www.cyberportal.net/werme  <>

[Feb 02, 2002] SPARC calling conventions & coroutines

From: [email protected] ([email protected]) Subject: SPARC calling conventions & coroutines Newsgroups: comp.sys.sun View: (This is the only article in this thread) | Original Format Date: 1990-06-05 21:07:39 PST

The following is a question concerning the SPARC architecture & the SunOS
support for the architecture.

I'm trying to port my C++ based threads package to a SPARC (Solbourne).
This is part of a multiprocessor simulation package for process oriented
discrete event simulation, written in G++. This code works on the
DECstation-3100, 68K based units, and in parallel on the Encore Multimax
(NS32K). So, I'm pretty certain the machine independent part works.

Threads are implemented via co-routines & private stacks. No stack copy is
done (too slow). The heart of the context switch on a SPARC looks like:

void
HardwareContext::magicSwitchTo(HardwareContext *to)
{
    asm("ta	%0" : : "I" (ST_FLUSH_WINDOWS));
    asm("st	%%sp,%0" : : "m" (sp));
    asm("st	%%fp,%0" : : "m" (fp));
    asm("ld	%0,%%sp" : : "m"(to -> sp));
    asm("ld	%0,%%fp" : : "m"(to -> fp));
    asm("ld	[%sp+60],%i7");	// prep return address
}

a ``HardwareContext'' represents a coroutine. ``to'' is the coroutine
to switch to. In assembly, this becomes:

.global _magicSwitchTo__15HardwareContextPT0
	.proc 1
_magicSwitchTo__15HardwareContextPT0:
	save %sp,-112,%sp
	ta	3
	st	%sp,[%i0]
	st	%fp,[%i0+4]
	ld	[%i1],%sp
	ld	[%i1+4],%fp
	ld	[%sp+60],%i7
	ret
	restore

An initial 3 stack contexts is built (by me), causing the initial ret to
``return'' to a thread entry routine; subsequent returns return to the
calling point.

I've read the SPARC architecture book that comes with the Sun doc's, but
have been having problems. I'm not entirely certain it's not related to
the g++ compiler I'm using, but...

The questions I'm after deal mainly with the way the FLUSH_WINDOWS trap
works, and when it's invoked, as well as the window restore/save code.

From the SPARC calling convention, I gather that on a save trap, the IN
and LOCAL registers are saved relative to the current SP, and that
preceding windows are saved by following the call chain and saving
relative to the SP.

QUESTION 1: when does this stop? i.e. if I ``fake'' call chains, how do I
   tell the save/restore code that this is ``the top of the stack'' and that
   no more window saves/restores should be done?  This isn't defined in the
   arch manual.

QUESTION 2: Does this imply that the current IN registers are also written
   to memory, or just previous IN registers? I'm assuming they are, which is
   why the ``prepping the return address' comment is there -- I need to pull
   the return address from the saved IN to return to the other thread. It
   doesn't work any differently if i put a  ``st %i7,[%sp+60]'' right after
   the ``ta 3'', so I'm assuming that this is already done.

QUESTION 3: I notice that setting breakpoints appears to flush the current
   IN and LOCAL's to memory, relative to %sp. Is this correct?  (I noticed
   this when single-stepping through the coroutine switch)

QUESTION 4: If the current IN window is flushed at breakpoints, when else
   is it flushed? e.g., at UNIX context switch time? If so,  than the
   previous code is bogus, because once I set the %sp, I might over-write the
   saved state of the ``to'' context. Not that the ``to'' context would use
   the in's or locals (other than %i7, the return address).

If anyone knows the answers of 1..4, please mail me. In particular, if
you've done something similar, please let me know -- my code seems to
work, but after >60K context switches, something goes bonkers. I'm curious
about question 4, because it might be that the ``to'' return address is
being overwritten on a UNIX process switch. That would be very annoying,
because it would require a more elaborate context switch mechanism of
pointing %sp to a ``dummy'' stack area, explicitly loading %i0..%i7 and
then setting %sp to the ``proper'' stack area.

Dirk Grunwald -- Univ. of Colorado at Boulder	([email protected])
					([email protected])

[Feb 02, 2002] The Great Debate by Randall Hyde (assembler vs. compiler generated code). Reminds me famous Cownay paper. compare also to Comp.compilers Re Assembly verses a high-level language.

• Great Debate I
• The Great Debate (Part II) - Economic Concerns
• The Great Debate (Part III) - Arithmetic
• The Great Debate (Part IY) - Fast Enough Isn't
• The Great Debate (Part Y) - Levels of Optimization

[Jan 12, 2002] VASM - Visual Assembler IDE good and up-to-date page by Thomas Jaeger.

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